K5A3X40YTC Datasheet, PDF (43/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
SRAM TIMING DIAGRAMS
Preliminary
MCP MEMORY
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS1_S
CS2_S
UB, LB
WE
Data in
Data out
tAS(3)
High-Z
Data Undefined
tWC
tCW(2)
tAW
tCW(2)
tBW
tWP(1)
tWR(4)
tWHZ
tDW
tDH
Data Valid
tOW
High-Z
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1_S Controlled)
Address
tAS(3)
tWC
tCW(2)
CS1_S
tAW
CS2_S
tWR(4)
UB, LB
WE
Data in
tBW
tWP(1)
tDW
tDH
Data Valid
Data out
High-Z
High-Z
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Revision 0.0
November 2002