K5A3X40YTC Datasheet, PDF (24/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Preliminary
MCP MEMORY
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 ball. DQ3 will go High if 50µs of the block erase time win-
dow expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been
accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device
executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the
Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase
Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase
Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the
device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation
from the program operation.
RY/BY : Ready/Busy
Flash memory has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If
the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept
any read/write or erase operation. When the RY/ BY ball is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If Flash memory is placed in an Erase Suspend mode, the RY/ BY output will be
High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse
sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase,
RY/ BY is also valid after the rising edge of the sixth WE pulse.
The ball is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required
for proper operation.
Vcc_F
Rp
Ready / Busy
open drain output
Vcc_F (Max.) - VOL (Max.)
Rp =
IOL + Σ IL
=
2.9V
2.1mA + Σ IL
where Σ IL is the sum of the input currents of all devices tied to the
Ready / Busy ball.
Vss
Device
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Revision 0.0
November 2002