K5A3X40YTC Datasheet, PDF(42/45 Page) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

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K5A3X40YTC Datasheet, PDF (42/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

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K5A3x40YT(B)C

Preliminary

MCP MEMORY

SRAM TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1S=OE=VIL, CS2S=WE=VIH, UB or/and LB=VIL)

tRC

Address

Data Out

tAA

tOH

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS1S

tRC

tAA

tOH

tCO1

CS2S

UB, LB

Data out

High-Z

tCO2

tBA

tOE

tOLZ

tBLZ

tLZ

Data Valid

tHZ

tBHZ

tOHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

- 42 -

Revision 0.0

November 2002

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