K5A3X40YTC Datasheet, PDF (35/45 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM

K5A3x40YT(B)C
Flash SWITCHING WAVEFORMS
Chip/Block Erase Operations
Preliminary
MCP MEMORY
Address
CE_F
OE
WE
DATA
RY/BY
555H
tAS
2AAH
tAH
555H
555H
2AAH
555H for Chip Erase
BA
tRC
tOES
tWC
tWP
tWPH
tCS
tDH
AAH
tDS
55H
80H
AAH
10H for Chip Erase
55H
30H
Vcc_F
tVCS
NOTE: BA : Block Address
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE Setup Time
CE_F Setup Time
Write Pulse Width
Write Pulse Width High
Read Cycle Time
Vcc_F Set Up Time
Symbol
tWC
tAS
tAH
tDS
tDH
tOES
tCS
tWP
tWPH
tRC
tVCS
70ns
Min
Max
70
-
0
-
45
-
35
-
0
-
0
-
0
-
35
-
25
-
70
-
50
-
80ns
Unit
Min
Max
80
-
ns
0
-
ns
45
-
ns
35
-
ns
0
-
ns
0
-
ns
0
-
ns
35
-
ns
25
-
ns
80
-
ns
50
-
µs
- 35 -
Revision 0.0
November 2002