K5T6432YT Datasheet, PDF (36/40 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 64M Bit 4Mx16 Four Bank NOR Flash Memory / 32M Bit 2Mx16 UtRAM

K5T6432YT(B)M
MCP MEMORY
UtRAM TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL)
Address
Data Out
tRC
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH)
Address
CS
UB, LB
OE
Data out
High-Z
tAA
tCO
tBA
tOE
tOLZ
tBLZ
tLZ
tRC1
tRC2
Data Valid
tOH
tHZ
tBHZ
tOHZ
(READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
3. The minimum read cycle(tRC) is determined later one of the tRC1 and tRC2.
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Revision 1.0
November 2001