K5T6432YT Datasheet, PDF (14/40 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 64M Bit 4Mx16 Four Bank NOR Flash Memory / 32M Bit 2Mx16 UtRAM

K5T6432YT(B)M
MCP MEMORY
Flash DEVICE OPERATION
The 64Mbit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine(WSM) control block
erase and word/page program operations. Operational modes are selected by the commands written to the Command User Inter-
face (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or
block erase operation.
A Deep Power Down mode is enabled when the F-RP pin is at Vss, minimizing power consumption.
Read Mode
The 64Mbit DINOR IV Flash Memory has four read modes, which accesses to the memory array, the Sequential Page Read, the
Device Identifier and the Status Register. The appropriate read commands are required to be written to the CUI. Upon initial device
power up or after exit from deep power down, the 64Mbit DINOR IV Flash Memory automatically resets to read array mode. In the
read array mode and in the conditions are low level input to OE, high level input to WE and F-RP, low level input to F-CE and
address signals to the address inputs (A21 - A0) the data of the addressed location to the data input/output (DQ15-DQ0) is output.
Standby Mode
When F-CE is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-
impedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and
the device consumes normal active power until the operation completes.
Output Disable
When OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state.
Automatic Power Down (APD)
The Automatic Power Down minimizes the power consumption during read mode. The device automatically turns to this mode when
any addresses or F-CE isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the
stand-by mode. During this mode, the output data is latched and can be read out. New data is read out correctly when addresses
are changed.
Deep Power Down
When F-RP is at VIL, the device is in the deep power down mode and its power consumption is substantially low. During read
modes, the memory is deselected and the data input/output are in a high-impedance (High-Z) state. After return from power down,
the CUI is reset to Read Array, and the Status Register is cleared to value 80H. During block erase or program modes, F-RP low will
abort either operation. Memory array data of the block being altered become invalid.
Write Mode
Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by bringing WE to low level and OE is at high level, while F-CE is at low
level. Address and data are latched on the earlier rising edge of WE and F-CE. Standard micro processor write timings are used.
Alternating Background Operation (BGO)
The 64Mbit DINOR IV Flash Memory allows to read array from one bank while the other bank operates in software command write
cycling or the erasing / programming operation in the background. Array Read operation with the other bank in BGO is performed by
changing the bank address without any additional command. When the bank address points the bank in software command write
cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same
as the normal read operation. BGO must be between Bank1, Bank2, Bank3, and Bank4.
Back Bank array Read (BBR)
In the 64Mbit DINOR IV Flash Memory , when one memory address is read according to a Read Mode in the case of the same as an
access when a Read Mode command is input, an another Bank memory data can be read out (Random or Sequential Mode) by
changing an another Bank address.
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Revision 1.0
November 2001