K5T6432YT Datasheet, PDF (19/40 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 64M Bit 4Mx16 Four Bank NOR Flash Memory / 32M Bit 2Mx16 UtRAM

K5T6432YT(B)M
MCP MEMORY
AC CHARACTERISTICS
Read / Write Mode (CE Control)
Parameter
Symbol
Write Cycle Time
tWC
Address Setup Time
tAS
Address Hold Time
tAH
Data Setup Time
tDS
Data Hold Time
tDH
OE Hold from WE High
tOEH
Write Enable Setup Time
tWS
Write Enable Hold Time
tWH
F-CE Pulse Width
tCEP
F-CE "H" Pulse Width
tCEPH
OE Hold to WE Low
tGHEL
Block Lock Setup to Write Enable High
tBLS
Block Lock Hold from Valid SRD
tBLH
Duration of Auto Program Operation (Word Mode) tDAP
Duration of Auto Program Operation (Page Mode) tDAP
Duration of Auto Block Erase Operation
tDAE
Delay Time to Begin Internal Operation
tEHRL
F-RP Recovery to F-CE Low
tPS
tAVAV
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
tWLEL
tEHWH
tELEH
tEHEL
tGHEL
tPHHWH
tQVPH
tWHRH1
tWHRH1
tWHRH2
tEHRL
tPHWL
Notes : 1. Timing measurements are made under AC waveforms for read operations
2. Typical values at F-Vcc=3.0V and Ta=25°C.
Vcc=2.7V~3.3V
Min
Typ
Max
85
35
0
35
0
10
0
0
35
30
85
85
0
30
300
4
80
150
600
90
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ns
ns
Program / Erase Time
Parameter
Block Erase Time
Main Block Write Time
Page Write Time
Flash to Page Buffer Time
Min
Typ
Max
Unit
150
600
ms
1
4
sec
4
80
ms
100
150
µs
Program Suspend / Erase Suspend Time
Parameter
Program Suspend Time
Erase Suspend Time
Min
Typ
Max
Unit
15
µs
15
µs
F-Vcc Power up / Down timing
Parameter
Min
Typ
Max
Unit
tVCS F-RP=VIH Setup Time from F-Vcc min.
2
15
µs
Please see 21 page.
During power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. The device must be
protected against initiation of write cycle for memory contents during power up / down. The delay time of min. 2 micro sec is always required
before read operation or write operation is initiated from the time F-Vcc reaches F-Vcc min. during power up /down. By holding F-RP=VIL, the
contents of memory is protected during F-Vcc power up / down. During power up, F-RP must be held VIL for min. 2us form the time F-Vcc
reaches F-Vcc min.. During power down, F-RP must be held VIL until F-Vcc reaches Vss. F-RP doesn’t have latch mode, therefore F-RP must be
held VIH during read operation or erase / program operation.
- 19 -
Revision 1.0
November 2001