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| K5T6432YT Datasheet, PDF (12/40 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 64M Bit 4Mx16 Four Bank NOR Flash Memory / 32M Bit 2Mx16 UtRAM | |||
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K5T6432YT(B)M
MCP MEMORY
Flash MEMORY COMMAND DEFINITION
Software lock release operation needs following consecutive 7bus cycles. Moreover, additional 127 bus cycles are needed for page
program operation.
Table 5. Command List (F-WP = VIH or VIL)
Setup Command for
Software Lock Release
Mode
1st Cycle
Address
Data1)
(DQ0-15)
Word Program
Write
Bank
60H
Page Program3)
Page Buffer to Flash
Write
Bank
60H
Write
Bank
60H
Block Erase / Confirm
Write
Bank
60H
Erase All Unlocked Blocks
Write
Bank
60H
Clear Page Buffer
Write
Bank
60H
Single Data Load to Page Buffer Write
Bank
60H
Flash to Page Buffer
Write
Bank
60H
Mode
Write
Write
Write
Write
Write
Write
Write
Write
2nd Cycle
Address
Data1)
(DQ0-15)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Mode
Write
Write
Write
Write
Write
Write
Write
Write
3rd Cycle
Address
Data1)
(DQ0-15)
Bank
ACH
Bank
ACH
Bank
ACH
Bank
ACH
Bank
ACH
Bank
ACH
Bank
ACH
Bank
ACH
Setup Command for
Software Lock Release
Word Program
Page Program3)
Page Buffer to Flash
Block Erase / Confirm
Erase All Unlocked Blocks
Clear Page Buffer
Single Data Load to Page Buffer
Flash to Page Buffer
Mode
Write
Write
Write
Write
Write
Write
Write
Write
4th Cycle
Address
Data1)
(DQ0-15)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Bank
Block6)
Mode
Write
Write
Write
Write
Write
Write
Write
Write
5th Cycle
Address
Data1)
(DQ0-15)
Bank
78H
Bank
78H
Bank
78H
Bank
78H
Bank
78H
Bank
78H
Bank
78H
Bank
78H
Setup Command for
Software Lock Release
Word Program
Page Program3)
Page Buffer to Flash
Block Erase / Confirm
Erase All Unlocked Blocks
Clear Page Buffer
Single Data Load to Page Buffer
Flash to Page Buffer
Mode
Write
Write
Write
Write
Write
Write
Write
Write
6th Cycle
Address
Data1)
(DQ0-15)
Bank
40h
Bank
41h
Bank
0Eh
Bank
20H
X
A7H
X
55H
Bank
74H
Bank
F1H
Mode
Write
Write
Write
Write
Write
Write
Write
Write
7th Cycle
Address
Data1)
(DQ0-15)
WA2)
WD2)
WA03)
WD03)
WA4)
D01)
BA5)
D01)
X
D01)
X
D01)
WA
WD
RA7)
D01)
8th-134th Cycle
Mode
Address
Data1)
(DQ0-15)
Write
WAn3)
WDn3)
Notes :
1. Upper byte data (DQ15-DQ8) is ignored.
2. WA=Write Address, WD=Write Data
3. WA0, WAn=Write Address, WD0, WDn=Write Data, Write address and write data must be provided sequentially from 00H to 7FH
for A6-A0. Page size is 128 words (128 word x 16 bit), and also A21-A7(block address, page address) must be valid.
4. WA=Write Address:A21-A7 (block address, page address) must be valid.
5. BA=Block Address:A21-A12(Bank1), A21-A15(Bank2, Bank3, Bank4)
6. Block=Block Address:A21-A15, Block=A21-A15
Address
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Block
Fixed0 A21
A20
A19
A18
A17
A16
A15
Block
Fixed0 A21
A20
A19
A18
A17
A16
A15
7. RA=Read Address: A21-A7 (block address, page address) must be valid.
- 12 -
Revision 1.0
November 2001
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