K5T6432YT Datasheet, PDF (16/40 Pages) Samsung semiconductor – Multi-Chip Package MEMORY 64M Bit 4Mx16 Four Bank NOR Flash Memory / 32M Bit 2Mx16 UtRAM

K5T6432YT(B)M
MCP MEMORY
Flash to Page Buffer Command (F1H/D0H)
Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm com-
mand of D0H. An address within the page to be loaded is required. Then the array data can be copied into the other pages within the
same bank by using the Page Buffer to Flash command.
Clear Page Buffer Command (55H/D0H)
Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of
D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from
another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and
allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The
device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and
Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the
Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume com-
mand of D0H is written to the CUI, the WSM will continue with the erase or program processes.
Data Protection
The 64M-bit DINOR(IV) Flash Memory has a master Write Protect pin (F-WP). When F-WP is at VIH, all blocks can be programmed
or erased. When F-WP is low, all blocks are in locked mode which prevents any modifications to memory blocks. Software Lock
Release function is only command which allows to program or erase. See the BLOCK LOCKING table on 13 page for details.
Power Supply Voltage
When the power supply voltage is less than VLKO, Low Vcc Lock-Out voltage, the device is set to the Read-only mode. Regarding
DC electrical characteristics of VLKO, see 18 page. A delay time of 2us is required before any device operation is initiated. The delay
time is measured from the time Vcc reaches Vccmin (2.7V). During power up, F-RP = Vss is recommended. Falling in Busy status is
not recommended for possibility of damaging the device.
Memory Organization
The 64Mbit DINOR IV Flash Memory is constructed by 2 boot blocks of 4K words, 6 parameter blocks of 4K words and 7 main
blocks of 32K words in Bank1, by 8 main blocks of 32K words in Bank2 and by 56 main blocks of 32K words in Bank3 and Bank4.
CAPACITANCE
Item
Symbol Test Condition
Min
Max
Unit
Input Capacitance
Output Capacitance
A21-A0, OE, WE, CS2.
F-CE, F-WP, F-RP
DQ15-DQ0, F-RY/BY
CIN
COUT
TA=25°C,
f=1MHz,
Vin=Vout=0V
8
pF
12
pF
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Revision 1.0
November 2001