7733 Datasheet, PDF (96/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

INTERRUPTS
4.8 Return from interrupt routine, 4.9 Multiple interrupts
4.8 Return from interrupt routine
When the RTI instruction is executed at the end of an interrupt routine, the contents of the program bank
register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack
area immediately before the INTACK sequence are automatically pulled. And then, a program returns to the
original routine and the suspended process is resumed.
Before the RTI instruction is executed, by executing the PUL instruction or others, make sure to pull
registers which were pushed by software in an interrupt routine. Make sure that the data length and register
length for the pull operation are equal to those for the push operation.
4.9 Multiple interrupts
When a program branches to an interrupt routine, the following occurs:
q Interrupt disable flag (I) = “1” (Interrupts are disabled.)
q Interrupt request bit of accepted interrupt = “0”
q Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt
Therefore, as long as the IPL remains unchanged, by clearing the interrupt disable flag (I) to “0” in an
interrupt routine, an interrupt request whose priority level is higher than the priority level of the interrupt
which is in progress can be accepted. In this way, multiple interrupts are processed.
Figure 4.9.1 shows how multiple interrupts are processed.
An interrupt request which is not accepted because its priority level is lower is held. When the RTI instruction
is executed, the interrupt priority level of the routine which was in progress at acceptance of an interrupt
request is pulled to the IPL. Therefore, if the following relationship is satisfied when interrupt priority level
detection is performed next, the held interrupt request is accepted.
Held interrupt request’s priority level > Processor interrupt priority level (IPL) which is pulled
7733 Group User's Manual
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