7733 Datasheet, PDF (92/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

INTERRUPTS
4.6 Interrupt priority level detection time
4.6 Interrupt priority level detection time
When the interrupt priority level detection time has passed after sampling starts, an interrupt request is
accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the
interrupt priority level detection time. Usually, select “2 cycles of φ” as the interrupt priority level detection
time.
(1) Interrupt priority detection time selection bits
b7 b6 b5 b4 b3 b2 b1 b0
0
Processor mode register 0 (address 5E 16)
b5, b4
Processor mode bits
Wait bit
Software reset bit
Interrupt priority detection time selection bits
0 0 _{7 cycles of clock [(a) shown below]}
0 1 4 cycles of clock [(b) shown below]
1 0 2 cycles of clock [(c) shown below]
1 1 Do not select.
Must be fixed to “0.”
Clock 1 output selection bit
(2) Interrupt priority level detection time
Op-code fetch cycle
Sampling pulse
(Note)
(a) 7 cycles
Interrupt priority level
detection time ^{(b) 4 cycles}
(c) 2 cycles
Note: This pulse resides when “2 cycles of ” is selected.
Fig. 4.6.1 Interrupt priority level detection time
7733 Group User's Manual
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