7733 Datasheet, PDF (557/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
Appendix 2. Memory allocation in SFR area
Address
Register name
Access characteristics
b7
b0
6016
Watchdog timer register
WO
6116 Watchdog timer frequency selection flag
6216
(Reserved area) ^g4
RW
6316
6416
6516
Memory allocation control register
UART 2 transmit/receive mode register
UART 2 baud rate register (BRG2)
RW
RW
WO
6616
6716
6816
6916
6A16
6B16
6C16
UART 2 transmission buffer register
UART 2 transmit/receive control register 0
UART 2 transmit/receive control register 1
UART 2 receive buffer register
Oscillation circuit control register 0
WO
WO
RO _RW
RO
R WR OR _W
RO
O
RO
RW(g2)
RW
6D16
Port function control register
RW
6E16
Serial transmit control register
RW
6F16
Oscillation circuit control register 1
WO
RW
7016 ^{A-D / UART 2 trans./rece. interrupt control register}
RW
7116 UART0 transmission interrupt control register
RW
7216 UART0 receive interrupt control register
RW
7316 UART1 transmission interrupt control register
RW
7416 UART1 receive interrupt control register
RW
7516
Timer A0 interrupt control register
RW
7616
Timer A1 interrupt control register
RW
7716
Timer A2 interrupt control register
RW
7816
Timer A3 interrupt control register
RW
7916
Timer A4 interrupt control register
RW
7A16
Timer B0 interrupt control register
RW
7B16
Timer B1 interrupt control register
RW
7C16
Timer B2 interrupt control register
RW
7D16
INT0 interrupt control register
RW
7E16
INT1 interrupt control register
RW
7F16 INT2/Key input interrupt control register
RW
State immediately after reset
b7
b0
? (g1)
?
0
?
?
0 0 00 0
?0 00 0 0 00
?
?
?
?
1 00 0
0 000 0 010
?
0 000 ^{000 ?}
? 000 0 0? 1
0 000 0 00 0
? ₀₀
?
0 ? 0 g3 0 0 0
?
0 00 0
?
0 00 0
?
0 00 0
?
0 00 0
?
0 000
?
0000
?
0 000
?
0 00 0
?
0 00 0
?
0 000
?
0000
?
0 000
?
0 000
? 00 0 000
? 00 0 000
? 00 0 000
g1 A value of “FFF16” is set to the watchdog timer. (Refer to chapter “10. WATCHDOG TIMER.”)
g2 For access characteristics at address 6C16, also refer to Figure 14.3.2.
g3 Fix this bit to “1” in the One Time PROM version and EPROM version.
(However, fix this bit to “0” in the 7735 Group.)
g4 Do not write to the reserved area.
(Refer to Figure 20.8.1 for the M37733S4BFP, M37733S4LHP, M37735S4BFP, 37735S4LHP.)
sInternal RAM area (M37733MHBXXXFP: addresses 8016 to FFF16)
At hardware reset
(not including the case where the stop or wait mode is terminated)...Undefined.
At software reset...Retains the state immediately before reset.
When the stop or wait mode is terminated
(when the hardware reset is used)...Retains the state immediately before the STP or WIT
instruction is executed.
Fig. 8 Memory allocation in SFR area (4)
7733 Group User’s Manual
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