7733 Datasheet, PDF (343/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

CONNECTING EXTERNAL DEVICES
12.3 Ready function
<<No wait>>
Sampling timing
Clock 1
CPU
E
ALE
RDY
Œ
Bus is not in use.

Ž

Bus is in use.
<<Wait 0>>
Sampling timing
Clock 1
CPU
E
ALE
RDY

Ž

Bus is in use.
<<Wait 1>>
Sampling timing
Clock 1
CPU
E
ALE
RDY

Ž

Bus is in use.
Œ “L” level which is input to pin RDY is
accepted, so that signal E is stopped
at “H” level for 1 cycle of clock 1
(area
), and CPU is stopped
at “L” level.
 “L” level which is input to pin RDY
is not accepted, but CPU is stopped at
“L” level.
Ž “L” level which is input to pin RDY
is accepted, so that signal E is stopped
at “L” level for 1 cycle of clock 1
(area
“L” level.
), and CPU is stopped at
 Ready state is terminated.
 “L” level which is input to pin RDY is not
accepted because it is sampled
immediately before a wait generated by
software (area
), but CPU is stopped
at “L” level.
Fig. 12.3.1 Timings when ready state is accepted and terminated
12–18
7733 Group User’s Manual