7733 Datasheet, PDF (239/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

SERIAL I/O
8.3 Clock synchronous serial I/O mode
UART0 transmit/receive mode register (address 30 16)
UART1 transmit/receive mode register (address 38 16)
UART2 transmit/receive mode register (address 64 16)
b7
0 !!!
b0
001
Clock synchronous serial I/O mode
Internal/External clock selection bit
0: Internal clock
1: External clock
! : It may be “0” or “1.”
Notes 1: Nothing is implemented to bit 7 of the UART2 transmit/receive
mode register.
UART0 transmit/receive control register 0 (address 34 16)
UART1 transmit/receive control register 0 (address 3C 16)
b7
b0
UART2 transmit/receive control register 0 (address 68 16)
b7
b0
BRG count source selection bits
b1b0
0 0: Clock f2
0 1: Clock f16
1 0: Clock f64
1 1: Clock f512
CTS / RTS function selection bit (Note 2)
0: The CTS function is selected. (The RTS function is disabled.)
1: The RTS function is selected.
CTS / RTS enable bit
0: The CTS / RTS function is enabled.
1: The CTS / RTS function is disabled.
CLK polarity selection bit
0: The receive data is input at the rising edge of the transfer clock.
1: The receive data is input at the falling edge of the transfer clock.
BRG count source selection bits
b1b0
0 0: Clock f2
0 1: Clock f16
1 0: Clock f64
1 1: Clock f512
CTS enable bit
0: The CTS function is enabled.
1: The CTS function is disabled (I/O port).
Transfer format selection bit
0: LSB first
1: MSB first
Clocks f2 , f16, f64, and f512 : Refer to chapter “14. CLOCK GENERATING CIRCUIT.”
Notes 2: The CTS / RTS function selection bit is valid
when the CTS / RTS enable bit = “0.”
The RTS function is ignored when an internal
clock is selected.
3: The RTS output function is not assigned for UART2.
UART0 baud rate register (BRG0) (address 31 16)
UART1 baud rate register (BRG1) (address 39 16)
UART2 baud rate register (BRG2) (address 65 16)
b7
b0
A value from 0016 to FF16 is set.
g Necessary only when an internal clock is selected.
Continued to
“Initial setting example for related registers when receiving (2)”
on the next page
Fig. 8.3.10 Initial setting example for related registers when receiving (1)
8–36
7733 Group User’s Manual