7733 Datasheet, PDF (569/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
Appendix 3. Control registers
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Timer A2 mode register (address 5816)
Timer A3 mode register (address 5916)
Timer A4 mode register (address 5A16)
Bit
Bit name
0 Operating mode selection
bits
1
2 Pulse output function
selection bit
Functions
b1 b0
0 1: Event counter mode
At reset _RW
0 _RW
0 _RW
0: No pulse is output. (Pin TA2OUT, TA3OUT, or 0
RW
TA4OUT functions as a programmable I/O
port.)
1: Pulse is output. (Pin TA2OUT, TA3OUT, or
TA4OUT functions as a pulse output pin.)
3 Count polarity selection bit 0: Counting is performed at the falling edge of 0 RW
the external signal.
1: Counting is performed at the rising edge of
the external signal.
4 Up-down switching factor
selection bit
0: Contents of the up-down flag
1: A signal which is input to pin TA2OUT,
TA3OUT, or TA4OUT
0 RW
5 Must be fixed to “0” in the event counter mode.
0 RW
6 Count type selection bit
0: Reload count type
1: Free-run count type
0 RW
7 Two-phase pulse signal
0: Normal processing
processing type selection 1: Quadruple processing
bit (Note)
0 _RW
Note: This bit is valid only for the timer A3 mode register.
For the timer A2 and A4 mode registers, this bit is ignored. (It may be “0” or “1.”)
(b15)
b7
(b8)
b0 b7
b0 _{Timer A2 register (addresses 4B16, 4A16)}
Timer A3 register (addresses 4D16, 4C16)
Timer A4 register (addresses 4F16, 4E16)
Bit
Functions
At reset RW
15 to 0 Values 000016 to FFFF16 can be set.
Assuming that the set value = n, counter
Undefined _RW
divides the count source frequency by (n + 1)
in down-counting, or by (FFFF16 – n + 1) in
up-counting.
At reading this register, the counter value is
read out.
7733 Group User’s Manual
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