7733 Datasheet, PDF (302/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

WATCHDOG TIMER
10.2 Operation description
10.2 Operation description
The watchdog timer’s operation is described below.
For its operation in the stop and wait modes, refer to chapter “11. STOP AND WAIT MODES.”
10.2.1 Basic operation
ŒThe watchdog timer starts counting down from “FFF16.”
When the watchdog timer’s most significant bit becomes “0,” in other words, when the countdown has
been performed 2048 times, a watchdog timer interrupt request occurs. (Refer to Table 10.2.1.)
ŽWhen the interrupt request occurs (), value “FFF16” is set to the watchdog timer.
The watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is
accepted, the processor interrupt priority level (IPL) is set to “1112.”
Table 10.2.1 Occurrence interval of watchdog timer interrupt request
Watchdog timer’s
count source
Occurrence interval of watchdog timer interrupt request
When system clock = When system clock = When system clock =
25 MHz (Note 1)
12 MHz (Note 1)
32 kHz (Note 2)
f512
41.9 ms
87.4 ms
32768 ms
f32
2.62 ms
5.46 ms
2048 ms
Clocks f32, f512, and system clock: Refer to chapter “14. CLOCK GENERATING CIRCUIT.”
Notes 1: This is applied when the system clock selection bit (bit 3 at address 6C16; Refer to Figure 10.2.1.)
= “0” and the main clock division selection bit (bit 0 at address 6F16; Refer to Figure 10.2.2.) = “0.”
2: This is applied when the port-Xc selection bit (bit 4 at address 6C16; Refer to Figure 10.2.1.) =
“1” and the system clock selection bit = “1.”
Make sure that dummy data must be written to address 6016 (Watchdog timer register) by software before
the most significant bit of the watchdog timer becomes “0.”
If writing to address 6016 is not performed because of a program runaway and the most significant bit of
the watchdog timer becomes “0,” a watchdog timer interrupt request occurs. This means that a program
runaway has occurred.
When resetting the microcomputer after detecting a program runaway, write “1” to the software reset bit
(bit 3 at address 5E16) in the watchdog timer interrupt routine. (Make sure that writing “1” to the software
reset bit must be performed on the condition that the main clock is stably supplied.) (For details, refer to
chapter “13. RESET” and section “17.3 Watchdog timer.”)
7733 Group User’s Manual
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