7733 Datasheet, PDF (581/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
Appendix 3. Control registers
Oscillation circuit control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Oscillation circuit control register 0 (address 6C16)
Bit
Bit name
0 XCOUT drivability selection bit
1 ^{Not implemented.}
Functions
0: Drivability “LOW”
1: Drivability “HIGH”
At reset RW
1 RW
(Note 1)
Un-
–
defined
2 ^{Main clock stop bit}
0: Main clock oscillation or external clock ₀
RW
input is available.
(Note 1)
1: Main clock oscillation or external clock
input is stopped.
3 System clock selection bit
When the port-Xc selection bit = “0,”
0: Main clock
1: Main clock divided by 8
When the port-Xc selection bit = “1,”
0: Main clock
1: Sub clock
0 RW
(Note 2)
4 ^{P ort-X c selection bit}
5 ^{System clock stop bit at wait state}
(Note 4)
0: Operate as I/O ports (P77, P76).
1: Operate as pins XCIN and XCOUT.
0: Operates in the wait mode.
1: Stopped in the wait mode.
0 ^RW
(Notes 2
and 3)
0 _RW
6 ^{Signal output disable selection bit}
0: Output is enabled. (Refer to Tables
1: Output is disabled. 12.1.2 and 12.1.5)
0
RW
7 Not implemented.
Un-
defined
–
Notes 1: Nothing can be written to this bit after reset. Writing to this bit is enabled when the port-Xc
selection bit = “1.”
2: When selecting the sub clock as the system clock, set bit 3 to “1” after setting bit 4 to “1.”
If the above settings are performed simultaneously, in other words, performed by
executing only one instruction, only bit 3 is set to “1.”
3: Although this bit can be set to “1,” it cannot be cleared to “0” after this bit is once set to “1.”
4: When setting the system clock stop bit at wait state to “1,” perform it immediately
before the WIT instruction is executed. Furthermore, clear this bit to “0” immediately after
the wait mode is terminated.
7733 Group User’s Manual
21-33