7733 Datasheet, PDF (721/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

ELECTRICAL CHARACTERISTICS
15.9 Memory expansion mode and Microprocessor mode : with wait 1
15.9 Memory expansion mode and Microprocessor mode : with wait 1
Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1), unless
otherwise noted)
g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted.
Symbol
tc
tw(H)
tw(L)
tr
tf
tsu(D–RDE)
th(RDE–D)
Parameter
External clock input cycle time (Note 2)
External clock input high-level pulse width (Note 3)
External clock input low-level pulse width (Note 3)
External clock rise time
External clock fall time
Data input setup time
Data input hold time
Limits
Min. Max. ^Unit
40
ns
15
ns
15
ns
8 ns
8 ns
32
ns
0
ns
Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2: When the main clock division selection bit = “1,” the minimum value of tc = 80 ns.
3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values
from 0.45 through 0.55.
Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note 1),
unless otherwise noted)
Symbol
td(CS–WE)
td(CS–RDE)
th(WE–CS)
th(RDE–CS)
td(An–WE)
td(An–RDE)
td(A–WE)
td(A–RDE)
th(WE–An)
th(RDE–An)
tw(ALE)
tsu(A–ALE)
th(ALE–A)
td(ALE–WE)
td(ALE–RDE)
td(WE–DQ)
Parameter
Chip-select output delay time
Chip-select hold time
Address output delay time
Address output delay time
Address hold time
ALE pulse width
Address output setup time
Address hold time
ALE output delay time
Data output delay time
Conditions
Data formula (Min.)
1 ! 10⁹
2• f(f2)
– 28
1 ! 10⁹
2• f(f2)
1 ! 10⁹
2• f(f2)
1 ! 10⁹
2• f(f2)
1 ! 10⁹
2• f(f2)
1 ! 10⁹
2• f(f2)
– 28
– 28
– 22
– 18
– 35
Fig. 15.11.1 in
part 1
Limits
Min.
Max.
12
4
12
12
18
22
5
9
4
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(WE–DQ)
tw(WE)
tpxz(RDE–DZ)
Data hold time
____ ____
WEL, WEH pulse width
Floating start delay time
1 ! 10⁹
2• f(f2)
4 ! 10⁹
2• f(f2)
– 22
– 30
18
130
ns
ns
5
ns
tpzx(RDE–DZ)
tw(RDE)
td(RSMP–WE)
td(RSMP–RDE)
th(φ 1–RSMP)
Floating release delay time
____
RDE pulse width
_____
RSMP output delay time
_____
RSMP hold time
1 ! 10⁹
2• f(f2)
– 20
20
ns
4 ! 10⁹
2• f(f2)
– 32
128
ns
1 ! 10⁹
2• f(f2) ^{– 30}
10
ns
0
ns
td(WE–φ 1)
td(RDE–φ 1)
φ 1 output delay time
0
18
ns
Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2: f(f2) represents the clock f2 frequency.
For the relationship with the main clock and sub clock, refer to Table 14.3.1.
7735 Group User’s Manual
15–7