7733 Datasheet, PDF (457/940 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATIONS
17.4 Power saving
(2) Initial settings for related registers
b7
b0
X
0111
Oscillation circuit control register 1 (address 6F 16)
An external clock is selected as the main clock.
Watchdog timer is not used when the stop mode is terminated.
An external clock is selected as the sub clock and P7 6 functions as a port.
Watchdog timer is not used when the stop mode is terminated.
In the one time PROM version or EPROM version of the 7733 Group, this bit
must be fixed to “1.” (In 7735 Group, this bit must be fixed to “0.” )
Must be fixed to “0.”
Note: When writing a value to this register, write a value of “55 16” by executing the LDM instruction,
and then write a desired value. (Refer to Figure 11.2.4.)
b7
11
b0
X _{Oscillation circuit control register 0 (address 6C 16)}
b7
000
XCIN-XCOUT is selected. (Sub clock is used.)
In the wait mode, clocks 2 to 512 are stopped.
b0
INT0 interrupt control register (address 7D 16)
Interrupt priority level is set. (Note that a value other than “000 2” is set.)
Interrupt request bit: 0 (Initialized)
An interrupt request occurs at the falling edge.
b7
b0
0
Timer B2 interrupt control register (address 7C 16)
b15
0316
Interrupt priority level is set. (Note that a value other than “000 2” is set.)
Interrupt request bit: 0 (Initialized)
b8 b7
FF16
b0
Timer B2 register (addresses 55 16 and 5416)
Interval of the clock timer’s interrupt request
occurrence: 1 second
Interrupt disable flag (I)
“0”: Interrupt is enabled.
b7
XXX
b0
0 1 0 1 _{Timer B2 mode register (address 5D 16)}
Settings for the clock timer
X: It may be “0” or “1.”
Fig. 17.4.4 Initial settings for related registers
17–50
7733 Group User’s Manual