HD6433694 Datasheet, PDF (421/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Item
15.3.1 I²C Bus Control
Register 1 (ICCR1)
Page Revision (See Manual for Details)
223
Bit Bit Name Description
3
CKS3
Transfer Clock Select 3 to 0
2
CKS2
These bits should be set according
1
CKS1
to the necessary transfer rate (see
table 15.2) in master mode. In slave
0
CKS0
mode, these bits are used for
reservation of the setup time in
transmit mode. The time is 10 t_cyc
when CKS3 = 0 and 20 t_cyc when
CKS3 = 1.
15.4.8 Example of Use 246
Figure 15.18 Sample
Flowchart for Master
Receive Mode
Figure 15.20 Sample
248
Flowchart for Slave
Receive Mode
Section 17 EEPROM
271
17.4.9 Read Operation
Figure 17.5 Current
Address Read Operation
Figure 17.6 Random
271
Address Read Operation
Supplementary explanation: When one byte is received, steps
[2] to [6] are skipped after step [1],
before jumping to step [7]. The step
[8] is dummy-read in ICDRR.
Supplementary explanation: When one byte is received, steps
[2] to [6] are skipped after step [1],
before jumping to step [7]. The step
[8] is dummy-read in ICDRR.
SCL
1 2 34 5 6 7891
89
SDA
D7
D0
Slave address
R/W ACK Read Data
Start
condition
Legend: R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
ACK
Stop
conditon
SCL
1 2 34 5 6 7891
89
SDA
D7
D0
Figure 17.7 Sequential
Read Operation (when
current address read is
used)
272
SCL
Start
condition
Slave address
R ACK
Read Data
ACK
Stop
conditon
1 2 34 5 6 7891
89
SDA
D7
D0
1
89
D7
D0
Slave address
R/W ACK Read Data ACK ^{. . . .}
Start
condition
Legend: R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Read Data ACK
Stop
conditon
Rev. 4.00, 03/04, page 393 of 400