HD6433694 Datasheet, PDF (314/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

20.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Register Name
—
Abbre-
viation
—
Low-voltage detection control register LVDCR
Low-voltage detection status register LVDSR
—
—
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable register
I²C bus status register
Slave address register
I²C bus transmit data register
I²C bus receive data register
—
ICCR1
ICCR2
ICMR
ICIER
ICSR
SAR
ICDRT
ICDRR
—
Timer mode register W
Timer control register W
Timer interrupt enable register W
Timer status register W
Timer I/O control register 0
Timer I/O control register 1
Timer counter
General register A
General register B
General register C
General register D
TMRW
TCRW
TIERW
TSRW
TIOR0
TIOR1
TCNT
GRA
GRB
GRC
GRD
Module
Bit No Address Name
— H'F000 to —
H'F72F
8
H'F730 LVDC*¹
8
H'F731 LVDC*¹
— H'F732 to —
H'F747
8
H'F748 IIC2
8
H'F749 IIC2
8
H'F74A IIC2
8
H'F74B IIC2
8
H'F74C IIC2
8
H'F74D IIC2
8
H'F74E IIC2
8
H'F74F IIC2
— H'F750 to —
H'FF7F
8
H’FF80 Timer W
8
H’FF81 Timer W
8
H’FF82 Timer W
8
H’FF83 Timer W
8
H’FF84 Timer W
8
H’FF85 Timer W
16 H’FF86 Timer W
16 H’FF88 Timer W
16 H’FF8A Timer W
16 H’FF8C Timer W
16 H’FF8E Timer W
Data
Bus Access
Width State
—
—
8
2
8
2
—
—
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
—
—
8
2
8
2
8
2
8
2
8
2
8
2
16*² 2
16*² 2
16*² 2
16*² 2
16*² 2
Rev. 4.00, 03/04, page 286 of 400