HD6433694 Datasheet, PDF (14/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

14.3.6 Serial Control Register 3 (SCR3) ........................................................................ 184
14.3.7 Serial Status Register (SSR) ................................................................................ 186
14.3.8 Bit Rate Register (BRR) ...................................................................................... 188
14.4 Operation in Asynchronous Mode .................................................................................... 195
14.4.1 Clock.................................................................................................................... 195
14.4.2 SCI3 Initialization................................................................................................ 196
14.4.3 Data Transmission ............................................................................................... 197
14.4.4 Serial Data Reception .......................................................................................... 199
14.5 Operation in Clocked Synchronous Mode ........................................................................ 203
14.5.1 Clock.................................................................................................................... 203
14.5.2 SCI3 Initialization................................................................................................ 203
14.5.3 Serial Data Transmission ..................................................................................... 204
14.5.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 206
14.5.5 Simultaneous Serial Data Transmission and Reception....................................... 208
14.6 Multiprocessor Communication Function......................................................................... 210
14.6.1 Multiprocessor Serial Data Transmission ............................................................ 211
14.6.2 Multiprocessor Serial Data Reception ................................................................. 212
14.7 Interrupts........................................................................................................................... 216
14.8 Usage Notes ...................................................................................................................... 217
14.8.1 Break Detection and Processing .......................................................................... 217
14.8.2 Mark State and Break Sending ............................................................................ 217
14.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 217
14.8.4 Receive Data Sampling Timing
and Reception Margin in Asynchronous Mode ................................................... 218
Section 15 I²C Bus Interface 2 (IIC2)................................................................ 219
15.1 Features............................................................................................................................. 219
15.2 Input/Output Pins.............................................................................................................. 221
15.3 Register Descriptions........................................................................................................ 221
15.3.1 I²C Bus Control Register 1 (ICCR1).................................................................... 222
15.3.2 I²C Bus Control Register 2 (ICCR2).................................................................... 224
15.3.3 I²C Bus Mode Register (ICMR)........................................................................... 225
15.3.4 I²C Bus Interrupt Enable Register (ICIER).......................................................... 227
15.3.5 I²C Bus Status Register (ICSR)............................................................................ 229
15.3.6 Slave Address Register (SAR)............................................................................. 231
15.3.7 I²C Bus Transmit Data Register (ICDRT) ........................................................... 232
15.3.8 I²C Bus Receive Data Register (ICDRR)............................................................. 232
15.3.9 I²C Bus Shift Register (ICDRS)........................................................................... 232
15.4 Operation .......................................................................................................................... 233
15.4.1 I²C Bus Format..................................................................................................... 233
15.4.2 Master Transmit Operation.................................................................................. 234
15.4.3 Master Receive Operation ................................................................................... 236
Rev. 4.00, 03/04, page xiv of xxviii