HD6433694 Datasheet, PDF (240/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Start transmission
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Set MPBT bit in SSR
Write transmit data to TDR
Yes
[2]
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
[1] Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
[2] To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
[3] To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
Clear TE bit in SCR3 to 0
<End>
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
14.6.2 Multiprocessor Serial Data Reception
Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
14.18 shows an example of SCI3 operation for multiprocessor format reception.
Rev. 4.00, 03/04, page 212 of 400