HD6433694 Datasheet, PDF (20/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 5.2 Block Diagram of System Clock Generator ................................................................ 68
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 68
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 68
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 69
Figure 5.6 Example of External Clock Input ................................................................................ 69
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 70
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 70
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 70
Figure 5.10 Pin Connection when not Using Subclock ................................................................ 71
Figure 5.11 Example of Incorrect Board Design ........................................................................... 72
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 78
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration............................................................................ 86
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 93
Figure 7.3 Program/Program-Verify Flowchart ........................................................................... 95
Figure 7.4 Erase/Erase-Verify Flowchart ..................................................................................... 98
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 103
Figure 9.2 Port 2 Pin Configuration............................................................................................ 108
Figure 9.3 Port 5 Pin Configuration............................................................................................ 111
Figure 9.4 Port 7 Pin Configuration............................................................................................ 116
Figure 9.5 Port 8 Pin Configuration............................................................................................ 119
Figure 9.6 Port B Pin Configuration........................................................................................... 123
Section 10 Timer A
Figure 10.1 Block Diagram of Timer A ..................................................................................... 126
Section 11 Timer V
Figure 11.1 Block Diagram of Timer V ..................................................................................... 132
Figure 11.2 Increment Timing with Internal Clock .................................................................... 138
Figure 11.3 Increment Timing with External Clock................................................................... 139
Figure 11.4 OVF Set Timing ...................................................................................................... 139
Figure 11.5 CMFA and CMFB Set Timing................................................................................ 139
Figure 11.6 TMOV Output Timing ............................................................................................ 140
Figure 11.7 Clear Timing by Compare Match............................................................................ 140
Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 140
Figure 11.9 Pulse Output Example ............................................................................................. 141
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 142
Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 143
Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 144
Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 144
Rev. 4.00, 03/04, page xx of xxviii