HD6433694 Datasheet, PDF (420/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

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Section 11 Timer V
140 ^ø
11.4.1 Timer V Operation
Figure 11.8 Clear Timing
by TMRIV Input
TMRIV(External
counter reset
input pin )
TCNTV reset
signal
TCNTV
N–1
N
H'00
Section 12 Timer W
157
12.4.1 Normal Operation
TCNT performs free-running or periodic counting operations.
After a reset, TCNT is set as a free-running counter. When the
CTS bit in TMRW is set to 1, TCNT starts incrementing the
count.
Figure 12.2 Free-Running 157, CST bit → CTS bit
Counter Operation
158
Figure 12.3 Periodic
Counter Operation
12.6 Usage Notes 5.,
172 Added
Figure 12.26 When
Compare Match and Bit
Manipulation Instruction to
TCRW Occur at the Same
Timing
Section 13 Watchdog
Timer
13.3 Operation
177 The internal reset signal is output for a period of 256 φ_OSC clock
cycles. TCWD is a writable counter, and when a value is set in
TCWD, the count-up starts from that value.
Figure 13.2 Watchdog 177 256 φ_OSC clock cycles
Timer Operation Example
Section 14 Serial
194
Communication Interface3
(SCI3)
14.3.8 Bit Rate Register
(BRR)
Bit Rate
(bit/s)
Operating Frequency φ (MHz)
20
n
N
Table 14.4 Examples of
2.5M
0
1
BRR Settings for Various
Bit Rates (Clocked
Synchronous Mode) (2)
Section 15 I²C Bus
Interface 2 (IIC2)
220 ICEIR → ICIER
15.1 Features
Figure 15.1 Block
Diagram of I²C Bus
Interface 2
Rev. 4.00, 03/04, page 392 of 400