HD6433694 Datasheet, PDF (196/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

φ
Input capture
signal
TCNT
GRA, GRB
N
N+1
M
N
N+1
GRC, GRD
M
N
Figure 12.20 Buffer Operation Timing (Input Capture)
12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 12.21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
N
N+1
GRA to GRD
N
Compare
match signal
IMFA to IMFD
IRRTW
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
Rev. 4.00, 03/04, page 168 of 400