HD6433694 Datasheet, PDF (108/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Table 6.3 Internal State in Each Operating Mode
Function
Subactive
Active Mode Sleep Mode Mode
Subsleep
Mode
Standby Mode
System clock oscillator
Functioning Functioning Halted
Halted
Halted
Subclock oscillator
Functioning Functioning Functioning Functioning Functioning
CPU
Instructions
operations _Registers
Functioning
Functioning
Halted
Retained
Functioning
Functioning
Halted
Retained
Halted
Retained
RAM
Functioning Retained
Functioning Retained
Retained
IO ports
Functioning Retained
Functioning Retained
Register
contents are
retained, but
output is the
high-impedance
state.
External IRQ3 to IRQ0 Functioning
interrupts _{WKP5 to WKP0 Functioning}
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Peripheral Timer A
functions
Functioning
Functioning
Functioning if the timekeeping time-base
function is selected, and retained if not selected
Timer V
Functioning Functioning Reset
Reset
Reset
Timer W
Functioning
Functioning
Retained (if internal clock φ is
selected as a count clock, the
counter is incremented by a
subclock*)
Retained
Watchdog timer Functioning
Functioning
Retained (functioning if the internal oscillator is
selected as a count clock*)
SCI3
Functioning Functioning Reset
Reset
Reset
IIC
Functioning Functioning Retained*
Retained
Retained
A/D converter Functioning Functioning Reset
Reset
Reset
Note: * Registers can be read or written in subactive mode.
6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1.
Rev. 4.00, 03/04, page 80 of 400