HD6433694 Datasheet, PDF (277/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

15.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of
each interrupt request.
Table 15.3 Interrupt Requests
Interrupt Request Abbreviation
Transmit Data Empty TXI
Transmit End
TEI
Receive Data Full
RXI
STOP Recognition STPI
NACK Receive
NAKI
Arbitration
Lost/Overrun
Interrupt Condition
(TDRE=1) ^• (TIE=1)
(TEND=1) ^• (TEIE=1)
(RDRF=1) ^• (RIE=1)
(STOP=1) ^• (STIE=1)
{(NACKF=1)+(AL=1)} ^•
(NAKIE=1)
Clocked
Synchronous
I²C Mode Mode
!
!
!
!
!
!
!
×
!
×
!
!
When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
Rev. 4.00, 03/04, page 249 of 400