HD6433694 Datasheet, PDF (201/432 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
Internal
oscillator
ø
CLK
PSS
TCSRWD
TCWD
TMWD
Legend:
TCSRWD: Timer control/status register WD
TCWD: Timer counter WD
PSS:
Prescaler S
TMWD: Timer mode register WD
Internal reset
signal
Figure 13.1 Block Diagram of Watchdog Timer
13.1 Features
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the
internal oscillator can be selected as the timer-counter clock. When the internal oscillator is
selected, it can operate as the watchdog timer in any operating mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
WDT0110A_000020020200
Rev. 4.00, 03/04, page 173 of 400