NS32CG16-10 Datasheet, PDF (8/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

2 0 Architectural Description (Continued)
FP Frame Pointer The FP register is used by a procedure
to access parameters and local variables on the stack The
FP register is set up on procedure entry with the ENTER
instruction and restored on procedure termination with the
EXIT instruction
The frame pointer holds the address in memory occupied by
the old contents of the frame pointer
SB Static Base The SB register points to the global vari-
ables of a software module This register is used to support
relocatable global variables for software modules The SB
register holds the lowest address in memory occupied by
the global variables of a module
INTBASE Interrupt Base The INTBASE register holds
the address of the dispatch table for interrupts and traps
(Section 3 2 1)
MOD Module The MOD register holds the address of the
module descriptor of the currently executing software mod-
ule The MOD register is 16 bits long therefore the module
table must be contained within the first 64 kbytes of memo-
ry
2 1 3 Processor Status Register
The Processor Status Register (PSR) holds status informa-
tion for the microprocessor
The PSR is sixteen bits long divided into two eight-bit
halves The low order eight bits are accessible to all pro-
grams but the high order eight bits are accessible only to
programs executing in Supervisor Mode
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B
I PSUNZ F J K L TC
FIGURE 2-2 Processor Status Register (PSR)
C The C bit indicates that a carry or borrow occurred after
an addition or subtraction instruction It can be used with
the ADDC and SUBC instructions to perform multiple-
precision integer arithmetic calculations It may have a
setting of 0 (no carry or borrow) or 1 (carry or borrow)
T The T bit causes program tracing If this bit is set to 1 a
TRC trap is executed after every instruction (Section
3 3 1)
L The L bit is altered by comparison instructions In a com-
parison instruction the L bit is set to ‘‘1’’ if the second
operand is less than the first operand when both oper-
ands are interpreted as unsigned integers Otherwise it
is set to ‘‘0’’ In Floating-Point comparisons this bit is
always cleared
K Reserved for use by the CPU
J Reserved for use by the CPU
F The F bit is a general condition flag which is altered by
many instructions (e g integer arithmetic instructions
use it to indicate overflow)
Z The Z bit is altered by comparison instructions In a com-
parison instruction the Z bit is set to ‘‘1’’ if the second
operand is equal to the first operand otherwise it is set
to ‘‘0’’
N The N bit is altered by comparison instructions In a
comparison instruction the N bit is set to ‘‘1’’ if the sec-
ond operand is less than the first operand when both
operands are interpreted as signed integers Otherwise
it is set to ‘‘0’’
U If the U bit is ‘‘1’’ no privileged instructions may be exe-
cuted If the U bit is ‘‘0’’ then all instructions may be
executed When Ue0 the processor is said to be in Su-
pervisor Mode when Ue1 the processor is said to be in
User Mode A User Mode program is restricted from exe-
cuting certain instructions and accessing certain regis-
ters which could interfere with the operating system For
example a User Mode program is prevented from
changing the setting of the flag used to indicate its own
privilege mode A Supervisor Mode program is assumed
to be a trusted part of the operating system hence it has
no such restrictions
S The S bit specifies whether the SP0 register or SP1 reg-
ister is used as the Stack Pointer The bit is automatical-
ly cleared on interrupts and traps It may have a setting
of 0 (use the SP0 register) or 1 (use the SP1 register)
P The P bit prevents a TRC trap from occurring more than
once for an instruction (Section 3 3 1) It may have a
setting of 0 (no trace pending) or 1 (trace pending)
I If Ie1 then all interrupts will be accepted If Ie0 only
the NMI interrupt is accepted Trap enables are not af-
fected by this bit
B Reserved for use by the CPU This bit is set to 1 during
the execution of the EXTBLT instruction and causes the
BPU signal to become active Upon reset B is set to
zero and the BPU signal is set high
Note 1 When an interrupt is acknowledged the B I P S and U bits are set
to zero and the BPU signal is set high A return from interrupt will
restore the original values from the copy of the PSR register saved
in the interrupt stack
Note 2 If BITBLT (BB) or EXTBLT instructions are executed in an interrupt
routine the PSR bits J and K must be cleared first
2 1 4 Configuration Register
The Configuration Register (CFG) is 8 bits wide of which
four bits are implemented The implemented bits are used to
declare the presence of certain external devices and to se-
lect the clock scaling factor CFG is programmed by the
SETCFG instruction The format of CFG is shown in Figure
2-3 The various control bits are described below
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0
CMF I
FIGURE 2-3 Configuration Register (CFG)
I Interrupt vectoring This bit controls whether maskable
interrupts are handled in nonvectored (Ie0) or vectored
(Ie1) mode Refer to Section 3 2 3 for more information
F Floating-point instruction set This bit indicates whether
a floating-point unit (FPU) is present to execute floating-
point instructions If this bit is 0 when the CPU executes
a floating-point instruction a Trap (UND) occurs If this
bit is 1 then the CPU transfers the instruction and any
necessary operands to the FPU using the slave-proces-
sor protocol described in Section 3 1 3 1
M Clock scaling This bit is used in conjuction with the C bit
to select the clock scaling factor
C Clock scaling Same as the M bit above Refer to Sec-
tion 3 4 3 on ‘‘Power Save Mode’’ for details
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