NS32CG16-10 Datasheet, PDF (46/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

3 0 Functional Description (Continued)
3 4 5 6 Slave Processor Bus Cycles
A Slave Processor bus cycle always takes exactly two clock
cycles labeled T1 and T4 (see Figures 3-21 and 3-22 ) Dur-
ing a Read cycle SPC is active from the beginning of T1 to
the beginning of T4 and the data is sampled at the end of
T1 The Cycle Status pins lead the cycle by one clock peri-
od and are sampled on the leading edge of SPC During a
Write cycle the CPU applies data and activates SPC at T1
removing SPC at T4 The Slave Processor latches the
status on the leading edge of SPC and latches data on the
trailing edge
The CPU does not pulse the Address Strobe (ADS) and no
bus signals are generated The direction of a transfer is de-
termined by the sequence (‘‘protocol’’) established by the
instruction under execution but the CPU indicates the direc-
tion on the DDIN pin for hardware debugging purposes
A Slave Processor operand is transferred in one or more
Slave bus cycles A Byte operand is transferred on the
least-significant byte of the Data Bus (AD0–AD7) and a
Word operand is transferred on the entire bus A Double
Word is transferred in a consecutive pair of bus cycles
least-significant word first A Quad Word is transferred in
two pairs of Slave cycles with other bus cycles possibly
occurring between them The word order is from least-signif-
icant word to most-significant
Figure 3-23 shows the NS32CG16 and FPU connection dia-
gram
TL EE 9424 – 31
Note Slave Processor samples Data Bus here
FIGURE 3-22 Slave Processor Write Cycle
3 4 5 7 Data Access Sequences
The 24-bit address provided by the NS32CG16 is a byte
address that is it uniquely identifies one of up to
16 777 216 8-bit memory locations An important feature of
the NS32CG16 is that the presence of a 16-bit data bus
imposes no restrictions on data alignment any data item
regardless of size may be placed starting at any memory
address The NS32CG16 provides a special control signal
High Byte Enable (HBE) which facilitates individual byte ad-
dressing on a 16-bit bus
Memory is organized as two 8-bit banks each bank receiv-
ing the word address (A1 – A23) in parallel One bank con-
nected to Data Bus pins AD0 – AD7 is enabled to respond
to even byte addresses i e when the least significant ad-
dress bit (A0) is low The other bank connected to Data Bus
pins AD8–AD15 is enabled when HBE is low See Figure
3-24
Any bus cycle falls into one of three categories Even Byte
Access Odd Byte Access and Even Word Access All ac-
cesses to any data type are made up of sequences of these
cycles Table 3-5 gives the state of A0 and HBE for each
category
Note CPU samples Data Bus here
TL EE 9424–30
FIGURE 3-21 Slave Processor Read Cycle
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