NS32CG16-10 Datasheet, PDF (37/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

3 0 Functional Description (Continued)
FIGURE 3-14 Recommended Reset Connections
TL EE 9424 – 23
TABLE 3-3 External Oscillator
Specifications Crystal Characteristics
Type
AT-Cut
Tolerance
0 005% at a25 C
Stability
0 01% from 0 C to a70 C
Resonance
20 MHz or 30 MHz
30 MHz
Fundamental (Parallel)
Third Overtone (Parallel)
Maximum Series Resistance
50X
Maximum Shunt Capacitance
7 pF
R C and L Values
Frequency R1 R2 C1 C2
C3
L
(MHz) (kX) (X) (pF) (pF) (pF) (mH)
20
270 75 20 20
30
180 51 20 20
30
180 51 20 20 800–1300 3 3
3 4 4 Resetting
The RSTI input pin is used to reset the NS32CG16 The
CPU samples RSTI on the falling edge of CTTL
Whenever a low level is detected the CPU responds imme-
diately Any instruction being executed is terminated any
results that have not yet been written to memory are dis-
carded and any pending interrupts and traps are eliminated
The internal latch for the edge-sensitive NMI signal is
cleared
On application of power RSTI must be held low for at least
50 ms after V_CC is stable This is to ensure that all on-chip
voltages are completely stable before operation Whenever
a Reset is applied it must also remain active for not less
than 64 CTTL cycles See Figures 3-15 and 3-16
3 4 3 Power Save Mode
The NS32CG16 provides a power save feature that can be
used to significantly reduce the power consumption at times
when the computational demand decreases The device
uses the clock signal at the OSCIN pin to derive the internal
clock as well as the external signals PHI1 PHI2 CTTL and
FCLK The frequency of these clock signals is affected by
the clock scaling factor Scaling factors of 1 2 4 or 8 can
be selected by properly setting the C- and M-bits in the CFG
register The power save mode should not be used to re-
duce the clock frequency below the minimum frequency re-
quired by the CPU
Upon reset both C and M are set to zero thus maximum
clock rate is selected
Due to the fact that the C- and M-bits are programmed by
the SETCFG instruction the power save feature can only be
controlled by programs running in supervisor mode
The following table shows the C- and M-bit settings for the
various scaling factors and the resulting supply current for a
crystal frequency of 30 MHz
Clock Scaling Factor vs Supply Current
C
M
Scaling
CPU Clock
Typical I_CC
Factor Frequency
at a5V
00
1
01
2
10
4
11
8
15 MHz
7 5 MHz
37 5 MHz
1 88 MHz
140 mA
76 mA
42 mA
25 mA
TL EE 9424 – 24
FIGURE 3-15 Power-On Reset Requirements
TL EE 9424 – 25
FIGURE 3-16 General Reset Timing
While in the Reset state the CPU drives the signals ADS
RD WR DBE TSO BPU and DDIN inactive AD0 – AD15
A16 – A23 and SPC are floated and the state of all other
output signals is undefined
The internal CPU clock PHI1 PHI2 and CTTL run at half the
frequency of the signal on the OSCIN pin
The HOLD signal must be kept inactive After the RSTI sig-
nal is driven high the CPU will stay in the reset condition for
approximately 8 clock cycles and then it will begin execution
at address 0
The PSR is reset to 0 The CFG C- and M-bits are reset to 0
FCLK runs at the same frequency as OSCIN NMI is en-
abled to allow Non-Maskable Interrupts The following con-
ditions are present after reset due to the PSR being reset
to 0
37