NS32CG16-10 Datasheet, PDF (26/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

3 0 Functional Description (Continued)
The Operand class columns give the Access Class for each
general operand defining how the addressing modes are
interpreted (see Series 32000 Instruction Set Reference
Manual)
The Operand Issued columns show the sizes of the oper-
ands issued to the Floating-Point Unit by the CPU ‘‘D’’ indi-
cates a 32-bit Double Word ‘‘i’’ indicates that the instruction
specifies an integer size for the operand (B e Byte
W e Word D e Double Word) ‘‘f’’ indicates that the in-
struction specifies a Floating-Point size for the operand
(F e 32-bit Standard Floating L e 64-bit Long Floating)
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it The
PSR Bits Affected column indicates which PSR bits if any
are updated from the Slave Processor Status Word (Figure
3-3)
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FIGURE 3-3 Slave Processor Status Word
Any operand indicated as being of type ‘‘f’’ will not cause a
transfer if the Register addressing mode is specified This is
because the Floating-Point Registers are physically on the
Floating-Point Unit and are therefore available without CPU
assistance
3 2 EXCEPTION PROCESSING
Exceptions are special events that alter the sequence of
instruction execution The CPU recognizes two basic types
of exceptions interrupts and traps
An interrupt occurs in response to an event signalled by
activating the NMI or INT input signals Interrupts are typi-
cally requested by peripheral devices that require the CPU’s
attention
Traps occur as a result either of exceptional conditions
(e g attempted division by zero) or of specific instructions
whose purpose is to cause a trap to occur (e g supervisor
call instruction)
When an exception is recognized the CPU saves the PC
PSR and the MOD register contents on the interrupt stack
and then it transfers control to an exception service proce-
dure
Details on the operations performed in the various cases by
the CPU to enter and exit the exception service procedure
are given in the following sections
It is to be noted that the reset operation is not treated here
as an exception Even though like any exception it alters
the instruction execution sequence
The reason being that the CPU handles reset in a signifi-
cantly different way than it does for exceptions
Refer to Section 3 4 4 for details on the reset operation
3 2 1 Exception Acknowledge Sequence
When an exception is recognized the CPU goes through
three major steps
1) Adjustment of Registers
Depending on the source of the exception the CPU may
restore and or adjust the contents of the Program Coun-
ter (PC) the Processor Status Register (PSR) and the
currently-selected Stack Pointer (SP) A copy of the PSR
is made and the PSR is then set to reflect Supervisor
Mode and selection of the Interrupt Stack
2) Vector Acquisition
A Vector is either obtained from the Data Bus or is sup-
plied by default
3) Service Call
The Vector is used as an index into the Interrupt Dis-
patch Table whose base address is taken from the CPU
Interrupt Base (INTBASE) Register See Figure 3-4 A
32-bit External Procedure Descriptor is read from the ta-
ble entry and an External Procedure Call is performed
using it The MOD Register (16 bits) and Program Coun-
ter (32 bits) are pushed on the Interrupt Stack
FIGURE 3-4 Interrupt Dispatch and Cascade Tables
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