NS32CG16-10 Datasheet, PDF (47/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

3 0 Functional Description (Continued)
TL EE 9424 – 73
FIGURE 3-23 NS32CG16 and FPU Interconnections
TL EE 9424 – 74
FIGURE 3-24 Memory Interface
TABLE 3-5 Bus Cycle Categories
Category
HBE
A0
Even Byte
1
0
Odd Byte
0
1
Even Word
0
0
Accesses of operands requiring more than one bus cycle
are performed sequentially with no idle T-states separating
them The number of bus cycles required to transfer an op-
erand depends on its size and its alignment (i e whether it
starts on an even byte address or an odd byte address)
Table 3-6 lists the bus cycles performed for each situation
For the timing of A0 and HBE see Section 3 4 5 2
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