NS32CG16-10 Datasheet, PDF (57/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

4 0 Device Specifications (Continued)
4 5 2 1 Output Signals Internal Propagation Delays NS32CG16-10 and NS32CG16-15 (Continued)
Name Figure
Description
Reference Conditions
NS32CG16-10
Min
Max
NS32CG16-15
Min
Max
Units
t_ALf
4-7 AD0–AD15 Floating
after R E CTTL Ti
(Caused by HOLD)
25
18
ns
t_AHf
t_ALnf
4-7
4-5 4-8
A16–A23 Floating
Address Bits 0–15
Not Floating
after R E CTTL Ti
after R E CTTL T1
25
18
ns
4
36
4
26
ns
t_AHnf
4-8 Address Bits 16–23
Not Floating
after R E CTTL T4
4
36
4
26
ns
t_Dv
4-6 4-10 Data Valid (Write Cycle) after R E CTTL T2 or T1
50
38
ns
t_Dh
4-6 4-10 Data Hold
after R E CTTL Next T1 or Ti 0
0
ns
t_ADSa
4-5 ADS Signal Active
after R E CTTL T1
5
35
5
26
ns
t_ADSia
4-5 ADS Signal Inactive
after F E CTTL T1
5
35
5
25
ns
t_ADSw
4-6 ADS Pulse Width
at 15% V_CC (Both Edges)
30
25
ns
t_ADSf
4-7 ADS Floating
after R E CTTL Ti
55
40
ns
t_ADSr
4-8 ADS Return from Floating after R E CTTL Ti
55
40
ns
t_ALADSs
4-6
Address Bits 0–15 Setup before ADS T E
25
18
ns
t_AHADSs 4-6 Address Bits 16 – 23 Setup before ADS T E
25
18
ns
t_ALADSh 4-5 Address Bits 0 – 15 Hold after ADS T E
12
12
ns
t_HBEv
4-5 HBE Signal Valid
after R E CTTL T1
60
38
ns
t_HBEh
4-5 HBE Signal Hold
after R E CTTL Next T1 or Ti 0
0
ns
t_HBEf
4-7 HBE Signal Floating
after R E CTTL Ti
55
40
ns
t_HBEr
4-8 HBE Return from Floating after R E CTTL Ti
55
40
ns
t_DDINv
4-5 DDIN Signal Valid
after R E CTTL T1
65
38
ns
t_DDINh
4-5 DDIN Signal Hold
after R E CTTL Next T1 or Ti 0
0
ns
t_DDINf
4-7 DDIN Floating
after R E CTTL Ti
55
40
ns
t_DDINr
4-8 DDIN Return from Floating after R E CTTL Ti
55
40
ns
t_SPCa
4-10 SPC Output Active
after R E CTTL T1
30
5
21
ns
t_SPCia
4-10 SPC Output Inactive
after R E CTTL T4
5
35
5
26
ns
t_SPCnf
4-12
SPC Output Non-Forcing
(Note 2)
after F E CTTL T4
t_CTp a 10
t_CTp a 8 ns
t_HLDAa
t_HLDAia
t_STv
4-7 HLDA Signal Active
4-8 HLDA Signal Inactive
4-5 Status ST0–ST3 Valid
after R E CTTL Ti
after R E CTTL Ti
after R E CTTL T4
(before T1 see Note 1)
50
28
ns
50
28
ns
45
38
ns
t_STh
4-5 Status ST0–ST3 Hold
after R E CTTL T4
0
0
ns
t_BPUv
4-5 BPU Signal Valid
after R E CTTL T4
45
30
ns
t_BPUh
4-5 BPU Signal Hold
after R E CTTL T4
5
5
ns
Note 1 Every memory cycle starts with T4 during which Cycle Status is applied If the CPU was idling the sequence will be ‘‘ Ti T4 T1 ’’ If the CPU was
not idling the sequence will be ‘‘ T4 T1 ’’
Note 2 If the CPU is connected directly to the FPU and the CTTL loading is not violated the CPU and FPU will function correctly together The CPU and FPU
connect directly without buffers They should be located less than 4 inches (10 centimeters) apart t_SPCa and t_SPCia will track each other on all CPU’s and therefore
it is not possible to have a minimum t_SPCia and a maximum t_SPCa value The pulse width minimum t_SPCw of the FPU will not be violated by the NS32CG16 when
connected directly to the FPU
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