NS32CG16-10 Datasheet, PDF (52/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

4 0 Device Specifications (Continued)
1100 Read for Effective Address
1101 Transfer Slave Operand
1110 Read Slave Status Word
1111 Broadcast Slave ID
US
User Supervisor
User or Supervisor Mode status High indicates
User Mode low indicates Supervisor Mode
ILO
Interlocked Operation
When active indicates that an interlocked oper-
ation is being executed
HLDA
Hold Acknowledge
Activated by the CPU in response to the HOLD
input to indicate that the CPU has released the
bus
PFS
Program Flow Status
A pulse on this signal indicates the beginning of
execution of an instruction
BPU
BPU Cycle
This signal is activated during a bus cycle to
enable an external BITBLT processing unit The
EXTBLT instruction activates this signal
RSTO
Reset Output
This signal becomes active when RSTI is low
initiating a system reset
RD
Read Strobe
Activated during CPU or DMAC read cycles to
enable reading of data from memory or periph-
erals See Section 3 4 5 2
WR
Write Strobe
Activated during CPU or DMAC write cycles to
enable writing of data to memory or peripherals
Note
BPU is low (Active) only during bus cycles involving
pre-fetching instructions and execution of EXTBLT
operands It is recommended that BPU ADS and
status lines (ST0–ST3) be used to qualify BPU bus
cycles If a DMA circuit exists in the system the
HLDA signal should be used to further qualify BPU
cycles BPU may become active during T4 of a non-
BPU bus cycle and may become inactive during T4
of a BPU bus cycle BPU must be qualified by ADS
and status lines (ST0–ST3) to be used as an exter-
nal gating signal
TSO
Timing State Output
The falling edge of TSO identifies the beginning
of state T2 of a bus cycle The rising edge iden-
tifies the beginning of state T4
DBE
Data Buffers Enable
Used to control external data buffers It is active
when the data buffers are to be enabled
OSCOUT
Crystal Output
This line is used as the return path for the crys-
tal (if used) When an external clock source is
used OSCOUT should be left unconnected or
loaded with no more than 5 pF of stray capaci-
tance
FCLK
Fast Clock
This clock is derived from the clock waveform
on OSCIN Its frequency is either the same as
OSCIN or is lower depending upon the scale
factor programmed into the CFG register
PHI1 PHI2 Two-Phase Clock
These outputs provide a two-phase clock with
frequency half that of FCLK They can be used
to clock the DP8510 DP8511 BPU The trace
lengths of PHI1 and PHI2 should be shorter
than 4 inches (10 centimeters) when connected
to the BPU
CTTL
System Clock
This clock is similar to PHI1 but has a much
higher driving capability The skew between its
rising edge and PHI1 rising edge is kept to a
minimum
4 1 4 Input-Output Signals
AD0 –15
Address Data Bus
Multiplexed Address Data information Bit 0 is
the least significant bit of each
SPC
Slave Processor Control
Used by the CPU as the data strobe output for
slave processor transfers used by a slave proc-
essor to acknowledge completion of a slave in-
struction See Section 3 4 5 6
DDIN
Data Direction
Status signal indicating the direction of the data
transfer during a bus cycle During HOLD ac-
knowledge this signal becomes an input and
determines the activation of RD or WR
ADS
Address Strobe
Controls address latches signals the beginning
of a bus cycle During HOLD acknowledge this
signal becomes an input and the CPU monitors
it to detect the beginning of a DMA cycle and
generate the relevant strobe signals When a
DMA is used ADS should be pulled up to V_CC
through a 10 kX resistor
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