NS32CG16-10 Datasheet, PDF (7/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

1 0 Product Introduction (Continued)
Below is a summary of the instructions that are directly ap-
plicable to graphics along with their intended use
Instruction
Application
BBAND
BBOR
BBFOR
BBXOR
BBSTOD
BITWT
EXTBLT
MOVMP
TBITS
SBITS
SBITPS
SBIT
CBIT
TBIT
IBIT
INDEX
The BITBLT group of instructions provide a
method of quickly imaging characters
creating patterns windowing and other
block oriented effects
Move Multiple Pattern is a very fast
instruction for clearing memory and drawing
patterns and lines
Test Bit String will measure the length of 1’s
or 0’s in an image supporting many data
compression methods (RLL) TBITS may
also be used to test for boundaries of
images
Set Bit String is a very fast instruction for
filling objects outline characters and
drawing horizontal lines
The TBITS and SBITS instructions support
Group 3 and Group 4 CCITT standards for
compression and decompression
algorithms
Set Bit Perpendicular String is a very fast
instruction for drawing vertical horizontal
and 45 lines
In printing applications SBITS and SBITPS
may be used to express portrait and
landscape respectively from the same
compressed font data The size of the
character may be scaled as it is drawn
The Bit group of instructions enable single
pixels anywhere in memory to be set
cleared tested or inverted
The INDEX instruction combines a multiply-
add sequence into a single instruction This
provides a fast translation of an X-Y
address to a pixel relative address
2 0 Architectural Description
2 1 REGISTER SET
The NS32CG16 CPU has 17 internal registers grouped ac-
cording to functions as follows 8 general purpose 7 ad-
dress 1 processor status and 1 configuration Figure 2-1
shows the NS32CG16 internal registers
Address
w 32 Bits x
General Purpose
w 32 Bits x
PC
R0
SP0
R1
SP1
R2
FP
R3
SB
R4
INTBASE
R5
MOD
R6
R7
Processor Status
Configuration
PSR
CFG
FIGURE 2-1 NS32CG16 Internal Registers
2 1 1 General Purpose Registers
There are eight registers (R0 – R7) used for satisfying the
high speed general storage requirements such as holding
temporary variables and addresses The general purpose
registers are free for any use by the programmer They are
32 bits in length If a general purpose register is specified for
an operand that is 8 or 16 bits long only the low part of the
register is used the high part is not referenced or modified
2 1 2 Address Registers
The seven address registers are used by the processor to
implement specific address functions Except for the MOD
register that is 16 bits wide all the others are 32 bits A
description of the address registers follows
PC Program Counter The PC register is a pointer to the
first byte of the instruction currently being executed The PC
is used to reference memory in the program section
SP0 SP1 Stack Pointers The SP0 register points to the
lowest address of the last item stored on the INTERRUPT
STACK This stack is normally used only by the operating
system It is used primarily for storing temporary data and
holding return information for operating system subroutines
and interrupt and trap service routines The SP1 register
points to the lowest address of the last item stored on the
USER STACK This stack is used by normal user programs
to hold temporary data and subroutine return information
When a reference is made to the selected Stack Pointer
(see PSR S-bit) the terms ‘‘SP Register’’ or ‘‘SP’’ are used
SP refers to either SP0 or SP1 depending on the setting of
the S bit in the PSR register If the S bit in the PSR is 0 SP
refers to SP0 If the S bit in the PSR is 1 then SP refers to
SP1
Stacks in the Series 32000 architecture grow downward in
memory A Push operation pre-decrements the Stack Point-
er by the operand length A Pop operation post-increments
the Stack Pointer by the operand length
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