NS32CG16-10 Datasheet, PDF (29/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

3 0 Functional Description (Continued)
FIGURE 3-7 Return from Interrupt (RETI) Instruction Flow
TL EE 9424 – 16
3 2 3 2 Vectored Mode Non-Cascaded Case
In the Vectored mode the CPU uses an Interrupt Control
Unit (ICU) to prioritize up to 16 interrupt requests Upon re-
ceipt of an interrupt request on the INT pin the CPU per-
forms an ‘‘Interrupt Acknowledge Master’’ bus cycle read-
ing a vector value from the low-order byte of the Data Bus
This vector is then used as an index into the Dispatch Table
in order to find the External Procedure Descriptor for the
proper interrupt service procedure The service procedure
eventually returns via the Return from Interrupt (RETI) in-
struction which performs an End of Interrupt bus cycle in-
forming the ICU that it may re-prioritize any interrupt re-
quests still pending The ICU provides the vector number
again which the CPU uses to determine whether it needs
also to inform a Cascaded ICU
In a system with only one ICU (16 levels of interrupt) the
vectors provided must be in the range of 0 through 127 that
is they must be positive numbers in eight bits By providing
a negative vector number an ICU flags the interrupt source
as being a Cascaded ICU (see below)
Note During a return from interrupt the CPU looks at Bit 7 of the vector
number from the master ICU If Bit 7 is 0 bits 0 through 6 are ignored
3 2 3 3 Vectored Mode Cascaded Case
In order to allow up to 256 levels of interrupt provision is
made both in the CPU and in the NS32202 Interrupt Control
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