NS32CG16-10 Datasheet, PDF (54/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

4 0 Device Specifications (Continued)
4 2 ABSOLUTE MAXIMUM RATINGS
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Temperature Under Bias
0 C to a70 C
Storage Temperature
b65 C to a150 C
All Input or Output Voltages with
Respect to GND
b0 5V to a7V
Note Absolute maximum ratings indicate limits beyond
which permanent damage may occur Continuous operation
at these limits is not intended operation should be limited to
those conditions specified under Electrical Characteristics
4 3 ELECTRICAL CHARACTERISTICS T_A e 0 C to a70 C V_CC e 5V g5% GND e 0V
Symbol
Parameter
Conditions
Min Typ
Max
Units
V_IH
V_IL
V_Ta
V_HYS
V_XL
V_XH
V_OH
V_OL
I_ILS
I_I
I_L
High Level Input Voltage
Low Level Input Voltage
RSTI Rising Threshold Voltage
RSTI Hysteresis Voltage
OSCIN Input Low Voltage
OSCIN Input High Voltage
High Level Output Voltage
Low Level Output Voltage
SPC Input Current (low)
Input Load Current
Leakage Current
Output and I O Pins in
TRI-STATE Input Mode
(Note 4)
(Note 3)
V_CC e 5 0V (Note 5)
V_CC e 5 0V (Note 5)
20
b0 5
25
08
I_OH e b400 mA (Note 6)
I_OL e 4 mA (Note 6)
V_IN e 0 4V SPC in Input Mode
0 ^s V_IN ^s V_CC All Inputs except SPC
0 4 ^s V_OUT ^s V_CC
45
24
0 05
b20
b20
V_CC a 0 5
V
08
V
35
V
18
V
05
V
V
V
0 45
V
10
mA
20
mA
20
mA
I_CC
Active Supply Current
I_OUT e 0 T_A e 25 C (Note 2)
140
200
mA
V_PH
PHI1 2 High Level Output Voltage I_OH e b400 mA
0 9 V_CC
V
V_PL
PHI1 2 Low Level Output Voltage I_OL e 4 mA
0 1 V_CC
V
Note 1 Care should be taken by designers to provide a minimum inductance path between the V_SS pins and system ground in order to minimize noise
Note 2 I_CC is affected by the clock scaling factor selected by the C and M bits in the CFG register see Section 3 2 1
Note 3 V_{IL min} in the range of b0 5V to b1 5V the pulse must be s 20 ns and the period between pulses t 120 ns
Note 4 V_{IH max} in the range of V_CC a 0 5V to V_CC a 2 0V the pulse must be s 25 ns and the period between pulses t 120 ns
Note 5 Not 100% tested
Note 6 All outputs except PHI1 and PHI2
54