NS32CG16-10 Datasheet, PDF (5/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

List of Illustrations (Continued)
Cycle Extension of a Read Cycle
3-20
Slave Processor Read Cycle
3-21
Slave Processor Write Cycle
3-22
NS32FX16 and FPU Interconnections
3-23
Memory Interface
3-24
HOLD Timing Bus Initially Idle
3-25
HOLD Timing Bus Initially Not Idle
3-26
Connection Diagram
4-1
Test Loading Configuration
4-2
Output Signals Specification Standard
4-3
Input Signals Specification Standard
4-4
Read Cycle
4-5
Write Cycle
4-6
HOLD Acknowledge Timing (Bus Initially Not Idle)
4-7
HOLD Timing (Bus Initially Idle)
4-8
External DMA Controller Bus Cycle
4-9
Slave Processor Write Timing
4-10
Slave Processor Read Timing
4-11
SPC Timing
4-12
PFS Signal Timing
4-13
ILO Signal Timing
4-14
Clock Waveforms
4-15
INT Signal Timing
4-16
NITI Signal Timing
4-17
Power-On Reset
4-18
Non-Power-On Reset
4-19
List of Tables
NS32FX16 Addressing Modes
2-1
NS32FX16 Instruction Set Summary
2-2
‘op’ and ‘i’ Field Encodings
2-3
Floating-Point Instruction Protocols
3-1
Summary of Exception Processing
3-2
External Oscillator Specifications
3-3
Interrupt Sequences
3-4
Bus Cycle Categories
3-5
Data Access Sequences
3-6
Basic Instructions
B-1
Floating-Point Instructions CPU Portion
B-2
Average Instruction Execution Times with No Wait-States
B-3
Average Instruction Execution Times with Wait-States
B-4
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