English
Language : 

NS32CG16-10 Datasheet, PDF (59/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor
◁
4 0 Device Specifications (Continued)
4 4 2 2 Input Signal Requirements NS32CG16-10 and NS32CG16-15
Name Figure
Description
Reference Conditions
tXp
4-15 OSCIN Clock Period
R E OSCIN to Next R E OSCIN
tXh
4-15 OSCIN High Time
(External Clock)
at 4 2V (Both Edges)
tXl
4-15 OSCIN Low Time
tDIs
4-5 4-11 Data In Setup
tDIh
4-5 4-11 Data In Hold
(see Note 1)
at 1 0V (Both Edges)
before R E CTTL T4
after R E CTTL T4
tCWs
tCWh
tWs
tWh
tHLDs
tHLDh
4-5 4-6
4-5 4-6
4-5 4-6
4-5 4-6
4-7 4-8
4-7 4-8
CWAIT Signal Setup
CWAIT Signal Hold
WAITn Signals Setup
WAITn Signals Hold
HOLD Setup Time
HOLD Hold Time
before R E CTTL T3 or T3(w)
after R E CTTL T3 or T3(w)
before R E CTTL T3 or T3(w)
after R E CTTL T3 or T3(w)
before R E CTTL TX2 or Ti
after R E CTTL Ti
tPWR
tRSTw
4-18
4-19
Power Stable to RSTI R E after VCC Reaches 4 5V
RSTI Pulse Width
at 0 8V (Both Edges)
tSPCh
4-12
SPC Hold Time
(see Note 3)
after R E CTTL
tINTh
4-16 INT Signal Hold
After R E CTTL T2 of Interrupt
Acknowledge Cycle
tNMIw
tSPCd
4-17
4-12
NMI Pulse Width
SPC Pulse Delay
from Slave
at 0 8V (Both Edges)
after F E CTTL T4
tSPCs
tADSs
tADSh
4-12
4-9
4-9
SPC Input Setup
ADS Input Setup
ADS Input Hold
(see Note 2)
before R E CTTL
before F E CTTL
after F E CTTL T1
tDDINs
4-9
DDIN Input Setup
before F E CTTL
tDDINh
4-9
DDIN Input Hold
after R E CTTL T4
Note 1 tDIh is always less than or equal to tRDia
Note 2 ADS must be deasserted before state T4 of the DMA controller cycle
Note 3 Not tested guaranteed by design
NS32CG16-10
Min
Max
50
500
16
16
18
7
20
5
20
5
30
0
50
64
0
8
70
2
25
15
10
15
7
NS32CG16-15
Min
Max
33
500
Units
ns
11
ns
11
ns
15
ns
7
ns
20
ns
5
ns
20
ns
5
ns
22
ns
0
ns
33
ms
64
tCTp
0
ns
8
tCTp
50
ns
2
tCTp
25
ns
10
ns
10
ns
10
ns
5
ns
59
 ▷