NS32CG16-10 Datasheet, PDF (56/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

4 0 Device Specifications (Continued)
4 5 2 Timing Tables
4 5 2 1 Output Signals Internal Propagation Delays NS32CG16-10 and NS32CG16-15
Name Figure
Description
Reference Conditions
NS32CG16-10
NS32CG16-15
(Note 3)
Units
Min
Max
Min
Max
t_CTp
4-15 CTTL Clock Period
R E CTTL to Next R E CTTL
100
1000
66
1000 ns
t_CTh
4-15 CTTL High Time
25 pF–100 pF Capacitive Load
At 1 5V (Both Edges)
0 42
0 57
0 41
0 58 t_CTp
(see Note 1)
t_CTl
4-15 CTTL Low Time
At 0 8V
25 pF–100 pF Capacitive Load ^{0 42}
0 56
0 41
0 53 t_CTp
t_CTr
t_CTf
t_{CLw(1 2)}
4-15
4-15
4-15
CTTL Rise Time
CTTL Fall Time
PHI1 PHI2 Pulse Width
0 8V to 2 0V V_CC on R E CTTL
0
2 0V to 0 8V V_CC on F E CTTL
0
At 2 0V on PHI1 PHI2
0 35
(Both Edges)
8
8
0 55
0
0
0 32
6
ns
6
ns
0 53 t_CTp
t_CLh
4-15 Clock High Time
At 90% V_CC on PHI1 PHI2
(Both Edges)
0 22
0 50
0 28
0 50 t_CTp
t_{nOVL(1 2)} 4-15 PHI1 PHI2 Non-Overlap At 50% V_CC on PHI1 PHI2
Time
2
2
ns
t_XFr
4-15 OSCIN to FCLK
R E Delay
80% V_CC on R E OSCIN
to R E FCLK
2
29
2
25
ns
t_FCr
4-15 FCLK to CTTL
R E Delay
R E FCLK to R E CTTL
b2
10
b2
10
ns
t_FCf
4-15 FCLK to CTTL
F E Delay
R E FCLK to F E CTTL
b2
10
b2
10
ns
t_PCr
t_ALv
t_ALh
t_AHv
t_AHh
t_ALfr
4-15 CTTL and PHI1 Skew
R E CTTL to R E PHI1
b4
4
b4
4
ns
4-5 Address Bits 0–15 Valid after R E CTTL T1
40
4
30
ns
4-5 Address Bits 0–15 Hold after R E CTTL T2
5
5
ns
4-5 Address Bits 16–23 Valid after R E CTTL T1
40
0
30
ns
4-5 Address Bits 16–23 Hold after R E CTTL Next T1 or Ti
0
0
ns
4-5 Address Bits 0–15
floating (during read)
after R E CTTL T2
5
38
5
28
ns
t_ALnfr
4-5 AD0–AD15
Floating (Note 2)
4
36
4
26
ns
Note 1 Device testing is performed using the Test Loading Characteristics in Table 4 1 Additional timing data for CTTL with various capacitive loads is not 100%
tested
Note 2 t_ALnfr is address bits 0–15 floating or not active after R E CTTL T1 This is only valid if the previous CPU cycle was a read (Figure 4 5) A previous write
may have ‘‘data’’ active into T1 of the next cycle which then becomes ‘‘address’’ during T1
Note 3 15 MHz specifications are only guaranteed when t_CTp e 66 ns
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