NS32CG16-10 Datasheet, PDF (67/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

4 0 Device Specifications (Continued)
FIGURE 4-16 INT Signal Timing
Note 1 Once INT is asserted it must remain asserted until it is acknowledged
Note 2 INTA is the Interrupt Acknowledge bus cycle (not a CPU signal) Refer to Section 3 4 5 and Table 3 4
TL EE 9424 – 79
FIGURE 4-17 NMI Signal Timing
TL EE 9424 – 51
FIGURE 4-18 Power-On Reset
TL EE 9424 – 53
67