NS32CG16-10 Datasheet, PDF (44/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

3 0 Functional Description (Continued)
3 4 5 4 Instruction Fetch Cycles
Instructions for the NS32CG16 CPU are ‘‘prefetched’’ that
is they are input before being needed into the next available
entry of the eight-byte instruction Queue The CPU performs
two types of instruction Fetch cycles Sequential and Non-
Sequential These can be distinguished from each other by
their differing status combinations on pins ST0–ST3 (Sec-
tion 3 4 5 1)
A Sequential Fetch will be performed by the CPU whenever
the Data Bus would otherwise be idle and the Instruction
Queue is not currently full Sequential Fetches are always
Even Word Read cycles (Table 3-5)
A Non-Sequential Fetch occurs as a result of any break in
the normally sequential flow of a program Any jump or
branch instruction a trap or an interrupt will cause the next
Instruction Fetch cycle to be Non-Sequential In addition
certain instructions flush the instruction queue causing the
next instruction fetch to display Non-Sequential status Only
the first bus cycle after a break displays Non-Sequential
status and that cycle is either an Even Word Read or an
Odd Byte Read depending on whether the distination ad-
dress is even or odd
3 4 5 5 Interrupt Control Cycles
Activating the INT or NMI pin on the CPU will initiate one or
more bus cycles whose purpose in interrupt control rather
than the tranfer of instructions or data Execution of the
Return from Interrupt Instruction (RETI) will also cause In-
terrupt Control bus cycles These differ from instruction or
data transfers only in the status presented on pins ST0 –
ST3 All Interrupt Control cycles are single-byte Read cy-
cles
Table 3-4 shows the Interrupt Control sequences associat-
ed with each interrupt and with the return from its service
routine For full details of the NS32CG16 interrupt structure
see Section 3 2
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