NS32CG16-10 Datasheet, PDF (64/82 Pages) National Semiconductor (TI) – High-Performance Printer / Display Processor

4 0 Device Specifications (Continued)
FIGURE 4-9 DMAC Initiated Bus Cycle
TL EE 9424 – 36
Note 1 ADS must be deactivated before state T4 of the DMA controller cycle
Note 2 During a DMA cycle WAIT1–2 must be kept inactive unless they are monitored by the DMA Controller A DMA cycle is similar to a CPU cycle The
NS32CG16 generates TSO RD WR and DBE The DMAC drives the address data lines HBE ADS and DDIN
Note 3 During a DMA cycle if the ADS signal is pulsed in order to initiate a bus cycle the HOLD signal must remain asserted until state T4 of the DMAC cycle
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