MC68HC908RF2 Datasheet, PDF (74/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Central Processor Unit (CPU)
Table 5-1. Instruction Set Summary (Sheet 2 of 7)
Source
Form
Operation
Description
Effect
on CCR
VH I NZC
BHCC rel
Branch if Half Carry Bit Clear
PC ← (PC) + 2 + rel ? (H) = 0
– – – – – – REL
28 rr
3
BHCS rel
Branch if Half Carry Bit Set
PC ← (PC) + 2 + rel ? (H) = 1
– – – – – – REL
29 rr 3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL
22 rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
PC ← (PC) + 2 + rel ? (C) = 0
– – – – – – REL
24 rr
3
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
– – – – – – REL
2F rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
– – – – – – REL
2E rr
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
(A) & (M)
IMM
DIR
EXT
0
–
–


–
IX2
IX1
IX
SP1
SP2
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 4
E5 ff
3
F5
2
9EE5 ff
4
9ED5 ee ff 5
BLE opr
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1 – – – – – – REL
93 rr
3
BLO rel
Branch if Lower (Same as BCS)
PC ← (PC) + 2 + rel ? (C) = 1
– – – – – – REL
25 rr
3
BLS rel
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL
23 rr
3
BLT opr
Branch if Less Than (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 – – – – – – REL
91 rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? (I) = 0
– – – – – – REL
2C rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? (N) = 1
– – – – – – REL
2B rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? (I) = 1
– – – – – – REL
2D rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? (Z) = 0
– – – – – – REL
26 rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? (N) = 0
– – – – – – REL
2A rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel
– – – – – – REL
20 rr
3
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
–
–
–
–
–

DIR (b3)
DIR (b4)
07
09
dd rr
dd rr
5
5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel
Branch Never
PC ← (PC) + 2
– – – – – – REL
21 rr
3
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
–
–
–
–
–

DIR (b3)
DIR (b4)
06
08
dd rr
dd rr
5
5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
Advance Information
74
Central Processor Unit (CPU)
MC68HC908RF2 — Rev. 1
MOTOROLA