MC68HC908RF2 Datasheet, PDF (105/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Break Module (BRK)
Functional Description
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Break Address Register
Bit 15
14
13
12
11
10
$FE0C
High (BRKH) Write:
See page 108.
Reset: 0
0
0
0
0
0
9
Bit 8
0
0
Read:
Break Address Register
Bit 7
6
5
4
3
2
1
Bit 0
$FE0D
Low (BRKL) Write:
See page 108.
Reset: 0
0
0
0
0
0
0
0
Read:
0
0
0
0
0
0
Break Status and Control
BRKE BRKA
$FE0E
Register (BSCR) Write:
See page 107.
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. I/O Register Summary
7.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status
bits can be cleared during the break state. The BCFE bit in the SIM break
flag control register (BFCR) enables software to clear status bits during
the break state. (See 6.8.3 SIM Break Flag Control Register and the
Break Interrupts subsection for each module.)
7.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
MC68HC908RF2 — Rev. 1
MOTOROLA
Break Module (BRK)
Advance Information
105