MC68HC908RF2 Datasheet, PDF (208/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module (TIM)
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0 percent duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100 percent duty cycle output. See 15.9.4 TIM
Channel Status and Control Registers.
15.6 Interrupts
These TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The timer counter value changes on
the falling edge of the internal bus clock. The timer overflow flag
(TOF) bit is set on the falling edge of the internal bus clock
following the timer rollover to $0000. The TIM overflow interrupt
enable bit, TOIE, enables TIM overflow interrupt requests. TOF
and TOIE are in the TIM status and control registers.
• TIM channel flag (CH0F) — The CH0F bit is set when an input
capture or output compare occurs on channel. Channel TIM CPU
interrupt requests are controlled by the channel interrupt enable
bit, CH1IE.
15.6.1 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
15.6.2 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
Advance Information
208
Timer Interface Module (TIM)
MC68HC908RF2 — Rev. 1
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