MC68HC908RF2 Datasheet, PDF (219/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module (TIM)
I/O Registers
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Register Name and Address: TCH0H—$0026
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
Indeterminate after reset
1
Bit 0
9
Bit 8
Register Name and Address: TCH0L—$0027
Bit 7
6
5
4
3
2
Read:
Bit 7
6
5
4
3
2
Write:
Reset:
Indeterminate after reset
1
Bit 0
1
Bit 0
Figure 15-9. TIM Channel 0 Registers (TCH0H and TCH0L)
Register Name and Address: TCH1H—$0029
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
Indeterminate after reset
1
Bit 0
9
Bit 8
Register Name and Address: TCH1L—$002A
Bit 7
6
5
4
3
2
Read:
Bit 7
6
5
4
3
2
Write:
Reset:
Indeterminate after reset
1
Bit 0
1
Bit 0
Figure 15-10. TIM Channel 1 Registers (TCH1H and TCH1L)
MC68HC908RF2 — Rev. 1
MOTOROLA
Timer Interface Module (TIM)
Advance Information
219