MC68HC908RF2 Datasheet, PDF (171/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
Functional Description
12.4.1 False Trip Protection
The V_DD pin level is digitally filtered to reduce false dead battery
detection due to power supply noise. For the LVI module to reset due to
a low-power supply, V_DD must remain at or below the V_LVR level for a
minimum 32–40 CGMXCLK cycles. See Table 12-1.
Table 12-1. LOWV Bit Indication
At Level:
V_DD > V_LVR
V_DD < V_LVR
V_DD < V_LVR
V_DD < V_LVR
V_DD
For Number of
CGMXCLK Cycles:
ANY
< 32 CGMXCLK cycles
Between 32 & 40 CGMXCLK
cycles
> 40 CGMXCLK cycles
Result
Filter counter remains
clear
No reset, continue
counting CGMXCLK
LVI may generate
a reset after
32 CGMXCLK cycles
LVI is guaranteed to
generate a reset
12.4.2 Short Stop Recovery Option
The LVI has an enable time of t_EN. The system stabilization time for
power-on reset and long stop recovery (both 4096 CGMXCLK cycles)
gives a delay longer than the LVI enable time for these startup scenarios.
There is no period where the MCU is not protected from a low-power
condition. However, when using the short stop recovery configuration
option, the 32 CGMXCLK delay must be greater than the LVI turn on
time to avoid a period in startup where the LVI is not protecting the MCU.
NOTE:
The LVI is enabled automatically after reset or stop recovery, if the
LVISTOP of the CONFIG register is set. (See Section 9. Configuration
Register (CONFIG).)
MC68HC908RF2 — Rev. 1
MOTOROLA
Low-Voltage Inhibit (LVI)
Advance Information
171